(1) Field of the Invention
This invention relates generally to semiconductor packages, and more particular, to electrical connections between semiconductor dies and the related substrate as part of the package.
(2) Description of the Prior Art
The present miniaturization trend in electronics towards higher-performance, smaller and lighter products has resulted in an increasing demand for smaller component packages and/or higher pin counts. The Ball Grid Array (BGA) concept has received much appreciation owing to its inherent, potential benefits to surface mount production. The BGA, taking advantage of the area under the package for the solder sphere interconnections, accommodates the increasing number of I/Os needed.
FIG. 1 prior art shows how a BGA package is composed of a chip 1, a BGA substrate 2, an interconnection 4 between said substrate 2 to a Printed Circuit Board (PCB) or motherboard 5 and a cover 6 to seal said package. Depending on the package style, the bare chip may be affixed to the BGA substrate 2 either face-up or facedown. The BGA substrate 2, which is really a miniature multi-layer Printed Circuit Board (PCB) with fine traces and microscopic through-hole vias, conveys the signals to the underlying printed circuit board 5 through an array of solder-bump attachments pads 4 on its bottom surface.
A cross-section of a typical prior art BGA is shown in FIG. 2 prior art, depicting a semiconductor chip 1, attached and wire-bonded to a BGA substrate 2. Wires 24 provide the connections between bond pads 27 on the semiconductor die I and wire landing pads or bond fingers 25 on the substrate 2. Leads as part of the bonding pattern 26 are provided to connect said wire-landing pads 25 to a through-hole via 23. Solder balls 20 are attached to the other side of the substrate 2 electrically connecting the circuitry of the BGA integrated circuit package to external circuitry on a printed circuit motherboard 5. A cover 6 is protecting said BGA. For lower pin counts, most often a two-sided substrate metallization is sufficient to provide electrical contact from wire-bonds through the plated through-holes to solder ball pads. In addition, thermal balls under the center of the package are often used to remove heat from the device through thermal vias 22.
FIG. 3 prior art shows a top view of another typical prior art implementation. A semiconductor chip I is attached to a substrate 2. In said prior art implementation solder balls are attached on the bottom of the substrate. They are connected by through-hole vias 23 and by leads 26 on the top surface of said substrate with the wire landing pads 25 on the top surface of said substrate 2. In order to avoid unnecessary complexity in FIG. 3 prior art only a few wire-landing pads are shown. Said through-hole vias 23 are located, as shown in FIG. 2 prior art, directly on top of said solder balls although this is not necessarily the case for all BGA technologies; if there are leads on the bottom side of the substrate the through-hole vias may be placed in a certain distance to the ball but this is not shown to avoid unnecessary complexity. Said wire landing pads 25 are located on the periphery of the substrate 2, outside of the ball grid, therefore requiring a significant length of all the bond wires 24 establishing the electrical connections between bond pads 31 on a chip 1 and said wire landing pads 25 on substrate 2. On the side of the chip 1 said wires are fastened on said bond pads 31. Said wires 24 have a significant length because all wire landing pads 25 on the substrate are located outside the ball grid array. A set of leads 26 are connecting said wire-landing pads 25 with said through-hole vias 23 as shown in FIG. 2 prior art. The length of said bond wires 24 is causing problems in the transmission of critical signals as e.g. high current signals, high-speed signals or high frequency signals.
With the general trend of miniaturization the length of said wires between the semiconductor chip and the substrate is causing more and more problems to the designers, especially for high current signals. The miniaturized spacing does not allow for wire landing pads in the via/ball array. Wire landing pads cannot be sized accordingly as the wire diameter shall not be reduced. Wires transporting high current signals must not exceed a critical wire length. There are prior art solutions having, as described, the wire landing pads of the bond wires outside the ball grid. This causes problems with wires being too long. Other solutions are having the landing pads inside the ball grid array close to the die. The disadvantage of this solution is that the grid array has been moved more far away from the semiconductor die and the package is consuming additional space on the motherboard and hence is too expensive. With the progress of miniaturization of semiconductor chips it is a growing challenge for the designers of electronic circuits to find a solution having short wires consuming minimal space on the motherboard.
U.S. Pat. No. (5,741,726 to Barber) describes a semiconductor device having external connections, including power supply connections such as to a power source or ground, is made without resort to wire landing pads. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wiring board and is divided into electrically insulated conductive segments. Each of the segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of wire landing pads, which serve to connect the semiconductor die to further external connections, such as signal connections.
U.S. Pat. No. (6,323,065 to Karnezos) discloses a semiconductor package arrangement including a heat spreader for dissipating heat and a ground plane having a first side that is attached to the heat spreader. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is attached to the ground plane, and the interconnect substrate has a complimentary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor arrangement. The package arrangement further includes at least one conductively filled via that is defined through the interconnect substrate and is in electrical contact with the ground plane to establish a direct ground connection from selected ones of the plurality of metal patterns of the interconnect substrate.
U.S. Pat. No. (6,389,689 to Heo) describes a method of fabricating a small-size multi-pin semiconductor package, which is as large as the semiconductor chip mounted thereon. Bond pads formed on semiconductor chip may be arranged at the center or at the edges of the upper surface of said semiconductor chip. A signal output from semiconductor chip is transmitted to a circuit pattern through a wire and then supplied to a motherboard through a solder ball.